Infineon Launches Integrated CMOS Read-Channel IC Chipset

15 May 2000

Infineon Technologies Launches Integrated CMOS Read-Channel IC Chipset for System-on-Chip Performance in Hard Disk Drives

    MUNICH, Germany--May 15, 2000--Infineon Technologies AG (FSE/NYSE:IFX), a leading semiconductor supplier to the mass storage market, today introduced Santa Cruz(TM), the first member of Infineon's high-performance System-on-Chip (SoC) read-channel IC family. Configurable as a stand-alone device or integration-ready core, the new read-channel IC boosts the capacity and retrieval speed of today's Hard Disk Drives (HDD), at a reduced end-user cost.
    The announcement represents another major step in Infineon's strategy to expand its system-on-chip activities. "Tapping into our broad intellectual property portfolio, Infineon is uniquely poised to take HDD system-on-chip (SoC) integration to the highest level," said Ruediger Stroh, Infineon's senior vice president of the Computer & Network Peripherals Group. "With the Santa Cruz read-channel IC, we have integrated a high-performance CMOS read channel with our microcontroller, customer ASIC and embedded DRAM. And we can manufacturer it in very high volumes with our world-class fab processes," Stroh added.
    To boost system performance required for next generation hard disk drives, the Santa Cruz IC supports fast access speeds up to 500 Mbits/s from a 0.25 micron CMOS implementation. In addition, the new read-channel IC features advanced trellis coding to improve BER (Bit Error Rate) performance in inherently noisy environments. This design produces SNR (Signal to Noise Ratio) gains of 1.5db over uncoded Extended Partial Response Equalization (EPR4) channels.
    Infineon has defined an architecture for its read-channel family that facilitates read-channel integration by moving many functions, traditionally in the analog domain, into the digital domain. One example is the fully digital timing recovery scheme that removes the Analog-to-Digital Converter (ADC) and FIR Filter from the timing loop. With this design, signal equalization can be performed entirely in the digital domain with the 9-tap FIR filter, allowing use of a simplified Continuous Time Filter (CTF).
    "The Santa Cruz read-channel IC will pave the way for our next generation of integrated read-channel devices," noted Mr. Stroh. "The company has a timetable to offer additional family member ICs to support the growing demands placed on next generation mass storage drives."
    Samples of Santa Cruz in a 100-pin TQFP package are now available, with 100K price at $3.40.