Silicon Metrics Introduces Timing Sign-Off Tool
8 May 2000
Silicon Metrics Introduces Timing Sign-Off Tool to Extend Static Timing Analysis; SiliconSmart TSO Eliminates Silicon Re-Spins Due to Hidden Timing Flaws
AUSTIN, Texas--May 8, 2000--Silicon Metrics Corporation today announced SiliconSmart TSO(TM)(a), a timing sign-off tool that allows users to selectively refine timing and obtain silicon-accurate timing results directly from popular static timing tools like Envisia(TM) Ambit(R) Synthesis from Cadence(R) (www.cadence.com).SiliconSmart TSO is the first product in a new generation of timing sign-off analysis tools designed to work with the company's OLA-compliant(b) libraries and other OLA-enabled design tools. SiliconSmart TSO uses the company's proprietary Selective Model Accuracy Refinement Technology(TM) (SMART) to produce the transistor-level accurate results required for timing sign-off. Tightly bound to Envisia Ambit tools through an OLA-compliant API, SiliconSmart TSO builds path models for the entire design. SiliconSmart TSO continues by automatically and selectively refining path models to the accuracy level that is required for achieving timing sign-off with confidence. Then, transistor-level accurate path models are backannotated to the static timing tool for further analysis.
One of the major benefits of the OLA-enabled flow is the removal of standard delay format (SDF) from the design flow, which simultaneously improves the overall design throughput. SiliconSmart TSO's integration with the Envisia Ambit synthesis and static timing tools (the first in a series of integration with design analysis tools) is the industry's first example of an OLA-compliant integration that breaks through the barrier of design tool interoperability. SiliconSmart TSO leverages its dynamic instance specific operating point (ISOP) models and SMART capability to produce path models with superior accuracy when compared to today's widely-used static, pre-defined operating point models. ISOP models remove 15 to 25 percent of the pessimism in cell transition delay (called slew rate or slew) typically found in static models. This enables designers to perform in situ critical path analysis, including the timing impact of on-chip voltage variations (IR drops) and significant temperature gradients.
"Accuracy and ease-of-use of timing tools are important issues for designers, and today timing sign-off remains a bottleneck to tapeout," said Carl Dobbs, principal designer and CEO of Silicon Group (Austin, Texas), a design services and IP integration company (www.silicongroup.com). "SiliconSmart TSO has the ability to add real value to a synthesis flow by bringing timing sign-off to the designer's desktop."
"We are very excited to see the level of interest in SiliconSmart TSO's ISOP handling," said Callan Carpenter, president and CEO of Silicon Metrics. "It is clear that removing standard delay format (SDF) from the design flow and simultaneously improving design throughput has caught the eye of many high-end VDSM designers. The delivery of this capability to the market marks the company's emergence as a center of technology excellence for timing sign-off."
Timing Accuracy Now Available at the Gate Level
In the past, designers typically simplified timing sign-off by separating the required timing models into two pieces: accurate, pre-design cell models and accurate, post-layout interconnect models. With today's VDSM designs, however, the cell and interconnect models share a complex non-linear interdependence. This interdependence invalidates the notion that timing sign-off can be accomplished by modeling cells and interconnect separately, performing path analysis, and finally resolving reported cell or interconnect timing violations in isolation. Before SiliconSmart TSO, designers had to resort to SPICE analysis of critical paths to uncover these problems. Now, designers can get the same level of accuracy productively within their gate-level design tool: a capability that promises to reduce design timing iterations by half.
"Silicon Metrics' timing sign-off product announcement underscores the momentum behind OLA for next generation tools and flows," said Andrew Graham, president of the Silicon Integration Initiative consortium. "SiliconSmart TSO showcases the value of OLA through its ability to collapse the designer's timing verification loop."
Pricing and Availability
General market release of SiliconSmart TSO is scheduled for Q3 2000. SiliconSmart TSO is available immediately on UNIX-based workstations from Sun(R) Microsystems. Term-based licensing for single-user and site configurations are being offered.
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