AXIOM Accelerates All Aspects of Functional Verification Including Breakthrough Testbench Parallelization

MILPITAS, Calif.--July 20, 2006--AXIOM Design Automation today announced that it has achieved a major milestone in improving functional verification performance by enabling SystemVerilog and OpenVera testbench parallelization. The testbench has long been the primary bottleneck in accelerating functional verification. AXIOM's MPSim is the only commercially available simulation product that can leverage multi-CPU hardware to accelerate all aspects of functional verification, including design, testbench, assertions, coverage and debugging.

"The industry is rapidly moving towards use of SystemVerilog and adoption of comprehensive testbench methodologies that allow constrained-random stimulus generation, automated checking and functional coverage," said Badru Agarwala, President and CEO of AXIOM. "With this trend taking hold, an increasing percentage of the simulation time is being consumed by testbench and less in design, even further exasperating the testbench performance bottleneck."

MPSim CTB (Compiled Testbench) can parallelize the testbench by partitioning it across multiple CPUs. This technology utilizes a combination of special features within SystemVerilog, such as multiple program scopes, and simple enhancements built around the OpenVera interface definitions using pragmas. The methodology is ideal for checkers, monitors and scoreboards and leads to significant acceleration of the overall simulation.

To learn more about this technology, users can attend the seminar entitled "Accelerating Function Verification Using Multi-CPU Technology" during the upcoming Design Automation Conference.

Availability

MPSim and Designer are available immediately. For more information, or to register for the seminar or a demo, please visit the AXIOM website at http://www.axiom-da.com .

About AXIOM

AXIOM is a pioneer in developing functional verification products. The company's mission is to accelerate the verification flow and to increase the overall productivity of verification engineers. The introduction of the MPSim multi-CPU simulator provides a quantum leap in verification performance to the industry and enables AXIOM to offer a complete solution to its customers. AXIOM's integrated verification environment combines the fastest simulator in the industry with advanced testbench automation, assertion based verification, debugging and coverage analysis to ensure that the most complex designs are verified in the least amount of time. AXIOM supports commercially available hardware and industry standard languages including SystemVerilog, Verilog and OpenVera to ensure continuity with your existing verification methodology while offering a clear path to immediate productivity improvement.